Lithography is a key step in the process of manufacturing semiconductor devices. In this step, radiation is projected through a mask so as to expose a layer of photoresist that has been deposited on the surface of a wafer. The pattern that is printed on the photoresist in this manner serves as a masking layer in forming circuit features on the wafer. Defects that may occur in the lithographic process are thus likely to cause defects in the corresponding circuit elements.
As the dimensions of integrated circuits decrease and patterns become more complex, defects and marginality in the features formed by lithography become increasingly problematic. To avoid (or at least minimize) defects in the integrated circuit device, the lithographic parameters, such as focal adjustment and exposure level, must be set precisely to the optimal values. The set of parameters that gives the best results, i.e., the smallest number of critical defects and the highest yield, is referred to as the “process window,” and systematic techniques for choosing these parameters are referred to generally as process window qualification.
Various methods for process window qualification have been described in the patent literature. For example, U.S. Pat. No. 6,902,855 describes a method of determining the presence of an anomaly in qualifying a pattern, patterning process, or patterning apparatus used in the fabrication of microlithographic patterns. Practicing this method on test wafers is said to enable the identification of spatial areas where a process will fail first and candidate regions for carrying out defect inspection and metrology.
Design information may be applied in analyzing the inspection data collected for the purpose of process window qualification. For example, U.S. Pat. No. 7,570,796, whose disclosure is incorporated herein by reference, describes methods and systems for utilizing design data in combination with inspection data, in which defects detected on a wafer are binned by comparing portions of design data proximate positions of the defects in design data space.